`timescale 1ns / 1ps

module status_machine_sim();
    reg clk = 1'b0;
    reg rst = 1'b0;
    reg [2:0] start = 'b0;
    reg [1:0] success = 'b0;

    wire [2:0] status;
    wire [2:0] substatus;

    status_machine UUT(
        clk,
        rst,
        start[0],
        start[1],
        start[2],
        success,

        status,
        substatus
    );

    always #1 begin clk = ~clk; end

    initial begin
        // RESET AT STATUS 5
        // NORMAL PROCESS
        #5 start = 'b001;
        #20 start = 'b010;
        #12 start = 'b000;
        #12 success = 2'b10; start = 'b100;
        #12 success = 2'b01;
        
        #20 rst = 1'b1;
        #10 rst = 1'b0;

        // ADDRESS WRONG INPUT
        #5 start = 'b001;
        #20 start = 'b010;
        #12 start = 'b000;
        #12 start = 'b100;
        
        #20 rst = 1'b1;
        #10 rst = 1'b0;
        
        // RESET AT STATUS 2
        #5 start = 'b001;
        #15 start = 'b010;
        #5 start = 'b000; rst = 1'b1;
        #10 rst = 1'b0;
        
        // WRONG BUTTON
        #10 start = 'b010;
        #5 start = 'b001;
        #5 start = 'b000;
        #15 start = 'b100;
        #10 start = 'b010;
        
        #10 $stop;
    end
endmodule
